PHENIC: Towards Photonic 3D-Network-on-Chip Architecture for High-throughput Many-core Systems-on-Chip

Network-on-chip architectures can improve the scalability, performance, and power efficiency of general multiprocessor systems and application-specific heterogeneous multicore and many-core SoCs (MCSoCs). This interconnection paradigm when combined with 3D integration technology offers advantages over 2D NoC design, such as shorter wire length, higher packing density, and smaller footprint. However, since processor architects and semiconductor industries are heading towards complex and large system design consisting of hundreds of PEs, traditional fully 2D or 3D electronic NoC approaches are becoming not enough for providing significant large bandwidth with low-power consumption. Optical Network-on-Chip (ONoC) promises significant advantages over their electronic counterparts. In particular, they offer a potentially disruptive technology solution with fundamentally low power dissipation that remains independent of capacity while providing ultra-high throughput and minimal access latency. In this work, we propose a pohotonic 3D-NoC architecture, named PHENIC, for High-throughput many-core Systems-onChip1. We present PHENIC’s architecture and the hardware design results of its path-setting layer. We also present preliminary study results of a photonic communication layer in a fair amount of details. Keywords-Optical Network-on-Chip; Many-core Systems-onChip; Architecture; High-throughput.